5762 search results - page 369 / 1153 » R-tree: A Hardware Implementation |
130
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ITC
2003
IEEE
16 years 2 days ago
2003
IEEE
At-speed test has become a requirement in IC technologies below 180 nm. Unfortunately, test mode switching activity and IR-drop present special challenges to the successful applic...
125
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FPL
2003
Springer
16 years 1 days ago
2003
Springer
This article describes the architecture and implementation of two systems on a programmable chip, which support high accuracy clock synchronization over Ethernet networks. The netw...
156
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DATE
2010
IEEE
15 years 12 months ago
2010
IEEE
—Associated with the ever growing integration scales is the increase in process variability. In the context of networkon-chip, this variability affects the maximum frequency that...
177
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
In this paper, we study and implement a routabilitydriven floorplanner with buffer block planning. It evaluates the routability of a floorplan by computing the probability that ...
149
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
After the discussion on the difference between floorplanning and packing in VLSI placement design, this paper adapts the floorplanner that is based on the Q-sequence to a packin...