5762 search results - page 365 / 1153 » R-tree: A Hardware Implementation |
150
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FPL
2007
Springer
16 years 29 days ago
2007
Springer
Designers of FPGA-based systems are increasingly including soft processors—processors implemented in programmable logic—in their designs. Any combination of area, clock freque...
158
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FPL
2007
Springer
16 years 29 days ago
2007
Springer
This paper presents a new approach to the FPGA implementation of image filters which are utilized to remove the saltand-pepper noise of high intensity (up to 70% of corrupted pix...
144
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ETS
2006
IEEE
16 years 26 days ago
2006
IEEE
This paper proposes a wrapper design for interconnects with guaranteed bandwidth and latency services and on-chip protocol. strate that these interconnects abstract the interconne...
167
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MTV
2006
IEEE
16 years 25 days ago
2006
IEEE
—Our Mutation-based Validation Paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently generate test sequences, we nee...
147
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ASYNC
2005
IEEE
16 years 13 days ago
2005
IEEE
This paper addresses the issue of Single-Event Upset (SEU) in quasi delay-insensitive (QDI) asynchronous circuits. We show that an SEU can cause abnormal computations in QDI circu...