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ICCAD
2002
IEEE
82views Hardware» more  ICCAD 2002»
16 years 3 months ago
Simplification of non-deterministic multi-valued networks
1 We discuss the simplification of non-deterministic MV networks and their internal nodes using internal flexibilities. Given the network structure and its external specification, ...
Alan Mishchenko, Robert K. Brayton
176
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ICCAD
2001
IEEE
113views Hardware» more  ICCAD 2001»
16 years 3 months ago
The Design and Optimization of SOC Test Solutions
1 We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip using Simulated Annealing. The produced results from the technique ar...
Erik Larsson, Zebo Peng, Gunnar Carlsson
ICCAD
2001
IEEE
95views Hardware» more  ICCAD 2001»
16 years 3 months ago
On the Signal Bounding Problem in Timing Analysis
In this paper, we study the propagation of slew dependent bounding signals and the corresponding slew problem in static timing analysis. The selection of slew from the latest arri...
Jin-fuw Lee, Daniel L. Ostapko, Jeffery Soreff, C....
ACSD
2009
IEEE
136views Hardware» more  ACSD 2009»
16 years 1 months ago
Model Checking Verilog Descriptions of Cell Libraries
We present a formal semantics for a subset of Verilog, commonly used to describe cell libraries, in terms of transition systems. Such transition systems can serve as input to symb...
Matthias Raffelsieper, Jan-Willem Roorda, Mohammad...
ISQED
2009
IEEE
70views Hardware» more  ISQED 2009»
16 years 1 months ago
Place and route considerations for voltage interpolated designs
— Voltage interpolation is a promising post fabrication technique for combating the effects of process variations. The benefits of voltage interpolation are well understood. It...
Kevin Brownell, Ali Durlov Khan, David Brooks, Gu-...