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ICCD
2002
IEEE
79views Hardware» more  ICCD 2002»
16 years 3 months ago
TAXI: Trace Analysis for X86 Interpretation
Although x86 processors have been around for a long time and are the most ubiquitous processors in the world, the amount of academic research regarding details of their performanc...
Stevan A. Vlaovic, Edward S. Davidson
ICCD
2001
IEEE
144views Hardware» more  ICCD 2001»
16 years 3 months ago
An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking
A new iterative multiplier based on a self-timed clocking scheme is presented. To reduce the area required for the multiplier, only two CSA rows are iteratively used to complete a...
Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park
ICCAD
2007
IEEE
115views Hardware» more  ICCAD 2007»
16 years 3 months ago
Timing optimization by restructuring long combinatorial paths
—We present an implementation of an algorithm for constructing provably fast circuits for a class of Boolean functions with input signals that have individual starting times. We ...
Jürgen Werber, Dieter Rautenbach, Christian S...
ICCAD
2006
IEEE
96views Hardware» more  ICCAD 2006»
16 years 3 months ago
Loop pipelining for high-throughput stream computation using self-timed rings
We present a technique for increasing the throughput of stream processing architectures by removing the bottlenecks caused by loop structures. We implement loops as self-timed pip...
Gennette Gill, John Hansen, Montek Singh
ICCAD
2002
IEEE
110views Hardware» more  ICCAD 2002»
16 years 3 months ago
Whirlpool PLAs: a regular logic structure and their synthesis
 A regular circuit structure called a Whirlpool PLA (WPLA) is proposed. It is suitable for the implementation of finite state machines as well as combinational logic. A WPLA is ...
Fan Mo, Robert K. Brayton