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ERSA
2004
129views Hardware» more  ERSA 2004»
15 years 8 months ago
A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs
Platform FPGAs incorporate many different components, such as processor core(s), reconfigurable logic, memory, etc., onto a single chip. When an application is synthesized on platf...
Jingzhao Ou, Viktor K. Prasanna
EUROPDS
1997
15 years 8 months ago
A Combined Virtual Shared Memory and Network which Schedules
In this paper, we follow a new path to arrive at the idea of a COMA — a Cache Only Memory Architecture. We show how the evolution of another architecture (ADARC) leads quite nat...
Ronald Moore, Bernd Klauer, Klaus Waldschmidt
IJES
2008
130views more  IJES 2008»
15 years 6 months ago
Deriving efficient control in Process Networks with Compaan/Laura
: At Leiden Embedded Research Center (LERC), we are building a tool chain called Compaan/Laura that allows us to map rapidly and efficiently signal processing applications written ...
Steven Derrien, Alexandru Turjan, Claudiu Zissules...
JUCS
2008
200views more  JUCS 2008»
15 years 6 months ago
Tabu Search on GPU
: Nowadays Personal Computers (PCs) are often equipped with powerful, multi-core CPU. However, the processing power of the modern PC does not depend only of the processing power of...
Adam Janiak, Wladyslaw A. Janiak, Maciej Lichtenst...
MAM
2006
95views more  MAM 2006»
15 years 6 months ago
Stochastic spatial routing for reconfigurable networks
FPGA placement and routing is time consuming, often serving as the major obstacle inhibiting a fast edit-compile-test loop in prototyping and development and the major obstacle pr...
André DeHon, Randy Huang, John Wawrzynek