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SBACPAD
2008
IEEE
126views Hardware» more  SBACPAD 2008»
16 years 1 months ago
A Software Transactional Memory System for an Asymmetric Processor Architecture
Due to the advent of multi-core processors and the consequent need for better concurrent programming abstractions, new synchronization paradigms have emerged. A promising one, kno...
Felipe Goldstein, Alexandro Baldassin, Paulo Cento...
CHES
2010
Springer
214views Cryptology» more  CHES 2010»
15 years 7 months ago
Correlation-Enhanced Power Analysis Collision Attack
Side-channel based collision attacks are a mostly disregarded alternative to DPA for analyzing unprotected implementations. The advent of strong countermeasures, such as masking, h...
Amir Moradi, Oliver Mischke, Thomas Eisenbarth
ISCA
2008
IEEE
136views Hardware» more  ISCA 2008»
15 years 6 months ago
A Randomized Queueless Algorithm for Breadth-First Search
First Come First Served is a policy that is accepted for implementing fairness in a number of application domains such as scheduling in Operating Systems [28, 11], scheduling web ...
K. Subramani, Kamesh Madduri
IOLTS
2007
IEEE
110views Hardware» more  IOLTS 2007»
16 years 1 months ago
An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding
In this paper we present an efficient design technique for implementing the Elliptic Curve Cryptographic (ECC) Scheme in FPGAs. Our technique is based on a novel and efficient i...
Osama Al-Khaleel, Christos A. Papachristou, Franci...
AHS
2006
IEEE
100views Hardware» more  AHS 2006»
16 years 25 days ago
Wormhole Routing with Virtual Channels using Adaptive Rate Control for Network-on-Chip (NoC)
This paper presents a new approach in realizing Virtual Channels tailored for Network on Chip implementations. The technique makes use of a flow control mechanism based on adaptiv...
Ioannis Nousias, Tughrul Arslan