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ISLPED
1998
ACM
84views Hardware» more  ISLPED 1998»
15 years 11 months ago
Low power architecture of the soft-output Viterbi algorithm
CT This paper investigates the low power implementation issues of the soft-output Viterbi algorithm (SOVA), a building block for turbo codes. By briefly explaining the theory of t...
David Garrett, Mircea R. Stan
ISCAS
1993
IEEE
133views Hardware» more  ISCAS 1993»
15 years 11 months ago
An efficient FIR filter architecture
– This paper describes an efficient architecture for FIR filters. By exploiting the reduced complexity made possible by the use of sparse powers-of-two coefficients, an FIR ...
Joseph B. Evans
ICCD
1992
IEEE
82views Hardware» more  ICCD 1992»
15 years 10 months ago
A Comparison of Self-Timed Design Using FPGA, CMOS, and GaAs Technologies
Asynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in ...
Erik Brunvand, Nick Michell, Kent F. Smith
ARC
2006
Springer
201views Hardware» more  ARC 2006»
15 years 10 months ago
Dynamic Partial Reconfigurable FIR Filter Design
Abstract. This paper presents a novel partially reconfigurable FIR filter design that employs dynamic partial reconfiguration. Our scope is to implement a low-power, area-efficient...
Yeong-Jae Oh, Hanho Lee, Chong Ho Lee
ISQED
2010
IEEE
126views Hardware» more  ISQED 2010»
15 years 8 months ago
Modeling and verification of industrial flash memories
We present a method to abstract, formalize, and verify industrial flash memory implementations. Flash memories contain specialized transistors, e.g., floating gate and split gate d...
Sandip Ray, Jayanta Bhadra, Thomas Portlock, Ronal...