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DATE
2006
IEEE
219views Hardware» more  DATE 2006»
16 years 25 days ago
Low cost LDPC decoder for DVB-S2
Because of its excellent bit-error-rate performance, the Low-Density Parity-Check (LDPC) algorithm is gaining increased attention in communication standards and literature. The ne...
John Dielissen, Andries Hekstra, Vincent Berg
DATE
2006
IEEE
98views Hardware» more  DATE 2006»
16 years 25 days ago
Test generation for combinational quantum cellular automata (QCA) circuits
— In this paper, we present a test generation framework for testing of quantum cellular automata (QCA) circuits. QCA is a nanotechnology that has attracted significant recent at...
Pallav Gupta, Niraj K. Jha, Loganathan Lingappan
ECBS
2003
IEEE
91views Hardware» more  ECBS 2003»
16 years 1 days ago
Modeling and Building Reliable, Re-Useable Software
Agile Software practices place great emphasis on coding, yet coding is time-consuming, difficult, and the source of many errors. The paper describes a way in which the specificati...
Ferdinand Wagner, Peter Wolstenholme
FCCM
2003
IEEE
210views VLSI» more  FCCM 2003»
16 years 1 days ago
Compact FPGA-based True and Pseudo Random Number Generators
Two FPGA based implementations of random number generators intended for embedded cryptographic applications are presented. The first is a true random number generator (TRNG) whic...
Kuen Hung Tsoi, K. H. Leung, Philip Heng Wai Leong
ITC
2003
IEEE
123views Hardware» more  ITC 2003»
16 years 1 days ago
A Comprehensive Approach to Assessing and Analyzing 1149.1 Test Logic
In this paper we introduce a tool which is capable of verifying an 1149.1 test logic implementation and its compliance to the IEEE 1149.1 Standard [1][2] while providing a precise...
Kevin Melocco, Hina Arora, Paul Setlak, Gary Kunse...