5762 search results - page 321 / 1153 » R-tree: A Hardware Implementation |
141
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ASPDAC
2004
ACM
16 years 5 days ago
2004
ACM
– This paper presents a high speed VLSI implementation of wavelet and golay error control codes. The design has been fabricated by MOSIS in a TSMC 0.25 µm CMOS process. Experime...
161
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CAV
2004
Springer
16 years 4 days ago
2004
Springer
This paper presents a symbolic model checking algorithm for Fixpoint Logic with Chop, an extension of the modal µ-calculus capable of defining non-regular properties. Some empiri...
148
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GLVLSI
2000
IEEE
15 years 11 months ago
2000
IEEE
Abstract - In this paper, we discuss hardware acceleration for real-time physical modeling that would allow for realistic virtual environments. Additionally, we propose algorithms ...
174
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DAGSTUHL
2006
15 years 8 months ago
2006
In this paper we outline two cryptoanalytic attacks against hardware implementation of the shrinking generator by Coppersmith et al., a classic design in low-cost, simple-design p...
155
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ETS
2000
IEEE
15 years 6 months ago
2000
IEEE
This paper outlines and discusses the pedagogical approach, the technical design architecture, and an innovative implementation of a collaborative role-play simulation technology ...