Sciweavers

5762 search results - page 319 / 1153
» R-tree: A Hardware Implementation
Sort
View
171
Voted
ASPLOS
2000
ACM
15 years 11 months ago
Evaluating Design Alternatives for Reliable Communication on High-Speed Networks
We systematically evaluate the performance of five implementations of a single, user-level communication interface. Each implementation makes different architectural assumptions ...
Raoul Bhoedjang, Kees Verstoep, Tim Rühl, Hen...
DAC
1994
ACM
15 years 10 months ago
MIST - A Design Aid for Programmable Pipelined Processors
-- In this paper, a tool to aid pipelined processor instruction set implementation is described. The purpose of the tool is to choose from among design alternatives a design that m...
Albert E. Casavant
FPL
2008
Springer
105views Hardware» more  FPL 2008»
15 years 8 months ago
Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems
A high-speed and secure dynamic partial reconfiguration (DPR) system is realized with AES-GCM that guarantees both confidentiality and authenticity of FPGA bitstreams. In DPR syst...
Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji T...
CASES
2008
ACM
15 years 8 months ago
Optimus: efficient realization of streaming applications on FPGAs
In this paper, we introduce Optimus: an optimizing synthesis compiler for streaming applications. Optimus compiles programs written in a high level streaming language to either so...
Amir Hormati, Manjunath Kudlur, Scott A. Mahlke, D...
ACMMSP
2006
ACM
252views Hardware» more  ACMMSP 2006»
16 years 22 days ago
Deconstructing process isolation
Most operating systems enforce process isolation through hardware protection mechanisms such as memory segmentation, page mapping, and differentiated user and kernel instructions....
Mark Aiken, Manuel Fähndrich, Chris Hawblitze...