5762 search results - page 311 / 1153 » R-tree: A Hardware Implementation |
165
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ASPDAC
2005
ACM
15 years 8 months ago
2005
ACM
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
154
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DAC
2005
ACM
15 years 8 months ago
2005
ACM
This paper presents an efficient hardware architecture of an on-chip logic minimization coprocessor. The proposed architecture employs TCAM cells to provide fastest and memory e...
191
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DATE
2005
IEEE
15 years 8 months ago
2005
IEEE
Developing a functional prototype of a system-on-chip provides a unifying vehicle for model validation and system refinement. Keeping the prototype executable everal abstraction l...
179
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ERSA
2007
15 years 8 months ago
2007
”C to Gates” compilers for FPGAs have been a topic of investigation for nearly two decades. Some of these endeavors have reached a point of viability. Impulse C, for example, ...
212
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ISCA
2012
IEEE
13 years 9 months ago
2012
IEEE
When multiple processor (CPU) cores and a GPU integrated together on the same chip share the off-chip main memory, requests from the GPU can heavily interfere with requests from t...