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FPL
2009
Springer
113views Hardware» more  FPL 2009»
15 years 11 months ago
Clock duplicity for high-precision timestamping in Gigabit Ethernet
Hardware-timestamping is essential for achieving tight synchronization in networking applications. This mechanism is selectively used on few high-cost tailored systems. Actual μP...
Carles Nicolau, Dolors Sala, Enrique Cantó
DATE
2000
IEEE
136views Hardware» more  DATE 2000»
15 years 11 months ago
Smart Antenna Receiver Based on a Single Chip Solution for GSM/DCS Baseband Processing
This paper presents a single chip implementation of a space-time algorithm for co-channel interference (CCI) and intersymbol interference (ISI) reduction in GSM/DCS systems. The t...
U. Girola, A. Picciriello, D. Vincenzoni
DATE
2000
IEEE
137views Hardware» more  DATE 2000»
15 years 11 months ago
Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language
This paper presents a methodology to retarget the technique of compiled simulation for Digital Signal Processors DSPs using the modeling language LISA. In the past, the principl...
Stefan Pees, Andreas Hoffmann, Heinrich Meyr
VTS
2000
IEEE
97views Hardware» more  VTS 2000»
15 years 11 months ago
A Low-Speed BIST Framework for High-Performance Circuit Testing
Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to...
Hans G. Kerkhoff, Mansour Shashaani, Manoj Sachdev
150
Voted
ISLPED
2000
ACM
91views Hardware» more  ISLPED 2000»
15 years 11 months ago
High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
A new high-speed Domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-o between performance and noise margins in conventional CD-Domino logic while dissipat...
Mohamed W. Allam, Mohab Anis, Mohamed I. Elmasry