5762 search results - page 299 / 1153 » R-tree: A Hardware Implementation |
168
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
Abstract—Behavioral synthesis is the compilation of an Electronic system-level (ESL) design into an RTL implementation. We present a suite of optimizations for equivalence checki...
156
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ASYNC
2002
IEEE
15 years 11 months ago
2002
IEEE
Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits ...
139
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
Future networked appliances should be able to download new services or upgrades from the network and execute them locally. This flexibility is typically achieved by processors tha...
155
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ISCAS
2002
IEEE
15 years 11 months ago
2002
IEEE
This paper presents a new self-resetting CMOS design for an Add-Compare-Select (ACS) unit, which is a key building block in a Viterbi decoder. Static CMOS and two-phase domino CMO...
168
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FPL
2009
Springer
15 years 11 months ago
2009
Springer
This paper presents an analytical model that relates FPGA architectural parameters to the expected speed of FPGA implementation. More precisely, the model relates the lookuptable ...