5762 search results - page 296 / 1153 » R-tree: A Hardware Implementation |
206
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ICCD
2003
IEEE
16 years 3 months ago
2003
IEEE
This paper introduces a new method for two-level logic minimization. Unlike previous approaches, the new method uses a SAT solver as an underlying engine. While the overall minimi...
165
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ICCAD
2003
IEEE
16 years 3 months ago
2003
IEEE
A new technique for the logic synthesis of asynchronous circuits is presented. It is based on the structural theory of Petri nets and integer linear programming. The technique is ...
169
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ICCAD
2001
IEEE
16 years 3 months ago
2001
IEEE
In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling a...
166
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—FPGAs are widely used for evaluating the error-floor performance of LDPC (low-density parity check) codes. We propose a scalable vector decoder for FPGA-based implementation of...
221
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DATE
2009
IEEE
16 years 1 months ago
2009
IEEE
—In this paper, a novel approach for integrating static non-preemptive software scheduling in formal bottom-up performance evaluation of embedded system models is described. The ...