Sciweavers

5762 search results - page 287 / 1153
» R-tree: A Hardware Implementation
Sort
View
ASPDAC
2000
ACM
131views Hardware» more  ASPDAC 2000»
15 years 10 months ago
Reconfigurable synchronized dataflow processor
- This paper describes the design and implementation of a reconfigurable synchronized dataflow processor (RSDP). The RSDP can configure its hardware to directly represent dataflow ...
Hiroshi Sasaki, Hitoshi Maruyama, Hideaki Tsukioka...
ICCD
1995
IEEE
121views Hardware» more  ICCD 1995»
15 years 10 months ago
Analysis of conditional resource sharing using a guard-based control representation
Optimization of hardware resources for conditional data-flow graph behavior is particularly important when conditional behavior occurs in cyclic loops and maximization of through...
Ivan P. Radivojevic, Forrest Brewer
APCCAS
2006
IEEE
269views Hardware» more  APCCAS 2006»
15 years 8 months ago
A Memory Bandwidth Optimized Interpolator for Motion Compensation in the H.264 Video Decoding
The paper presents an interpolator design for motion compensation used in the H.264 video decoding. The presented design is optimized according to the available data bandwidth to a...
Tzu-Yun Kuo, Yu-Kun Lin, Tian-Sheuan Chang
FPGA
2009
ACM
201views FPGA» more  FPGA 2009»
16 years 1 months ago
A high-performance FPGA architecture for restricted boltzmann machines
Despite the popularity and success of neural networks in research, the number of resulting commercial or industrial applications have been limited. A primary cause of this lack of...
Daniel L. Ly, Paul Chow
EH
2002
IEEE
81views Hardware» more  EH 2002»
15 years 11 months ago
Self-Assembling Circuits with Autonomous Fault Handling
This paper reports on the results of our recent NASA SBIR contract, “Autonomous Self-Repairing Circuits,” in which we developed a novel approach to fault-tolerant circuit synt...
Nicholas J. Macias, Lisa J. K. Durbeck