5762 search results - page 269 / 1153 » R-tree: A Hardware Implementation |
173
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ICCAD
2009
IEEE
15 years 4 months ago
2009
IEEE
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs ...
215
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IPPS
2010
IEEE
15 years 3 months ago
2010
IEEE
Very Long Instruction Word (VLIW) processors are a popular choice in embedded domain due to their hardware simplicity, low cost and low power consumption. Simultaneous MultiThreadi...
157
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TVLSI
2010
15 years 1 months ago
2010
Hardware debuggers and logic analyzers must be able to record a continuous trace of data. Since the trace data are tremendous, to save space, these traces are often compressed. The...
196
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CISS
2010
IEEE
14 years 10 months ago
2010
IEEE
Abstract—Compressive sampling (CS) has emerged as significant signal processing framework to acquire and reconstruct sparse signals at rates significantly below the Nyquist rate...
199
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ASPDAC
2011
ACM
2011
ACM
A structured parallel periodic Arnoldi shooting algorithm for RF-PSS analysis based on GPU platforms
14 years 10 months ago
The recent multi/many-core CPUs or GPUs have provided an ideal parallel computing platform to accelerate the timeconsuming analysis of radio-frequency/millimeter-wave (RF/ MM) int...