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FCCM
2007
IEEE
168views VLSI» more  FCCM 2007»
15 years 6 months ago
Discrete-Time Cellular Neural Networks in FPGA
This paper describes a novel architecture for the hardware implementation of non-linear multi-layer cellular neural networks. This makes it feasible to design CNNs with millions o...
J. Javier Martínez-Álvarez, F. Javie...
ISMAR
2007
IEEE
16 years 28 days ago
Accelerating Template-Based Matching on the GPU for AR Applications
Recently researchers have shown that it is possible to use GPU hardware for image processing and computer vision algorithms. We have been exploring how to use GPU hardware to impr...
Yannick Allusse, Raphael Grasset, Mark Billinghurs...
ASYNC
2004
IEEE
107views Hardware» more  ASYNC 2004»
15 years 10 months ago
A Fast and Energy-Efficient Stack
We present some novel hardware implementations of a stack. All designs are clockless, fast, and energy efficient, while occupying modest area. We implemented a 42-place stack chip...
Jo C. Ebergen, Daniel Finchelstein, Russell Kao, J...
ETS
2002
IEEE
139views Hardware» more  ETS 2002»
15 years 6 months ago
Automated Tutorial and Assignment Assessment
Computer simulation is used extensively both as an educational tool and within industry. It can be employed as a means of developing a new process or system or as a means of exper...
Roger F. Browne
SIGMETRICS
2002
ACM
106views Hardware» more  SIGMETRICS 2002»
15 years 6 months ago
Analysis of methods for scheduling low priority disk drive tasks
This paper analyzes various algorithms for scheduling low priority disk drive tasks. The derived closed form solution is applicable to class of greedy algorithms that include a va...
Eitan Bachmat, Jiri Schindler