5762 search results - page 247 / 1153 » R-tree: A Hardware Implementation |
164
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CHES
1999
Springer
15 years 11 months ago
1999
Springer
Cryptographic algorithms are more efficiently implemented in custom hardware than in software running on general-purpose processors. However, systems which use hardware implementat...
146
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ASPDAC
2010
ACM
15 years 4 months ago
2010
ACM
Multi-operand adders, which are also found in parallel multipliers, usually consist of the compression trees which reduce the number of operands per a bit to two, and the carrypro...
207
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SOCA
2010
IEEE
15 years 4 months ago
2010
IEEE
While modern CPUs offer an increasing number of cores with shared caches, prevailing execution engines for business processes, workflows, or Web service compositions have not been ...
252
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ASAP
2011
IEEE
2011
IEEE
High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder
14 years 6 months ago
—To meet the higher data rate requirement of emerging wireless communication technology, numerous parallel turbo decoder architectures have been developed. However, the interleav...
141
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CHES
2006
Springer
15 years 10 months ago
2006
Springer
In this paper, we propose a new block cipher HIGHT with 64-bit block length and 128-bit key length. It provides low-resource hardware implementation, which is proper to ubiquitous ...