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MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
15 years 5 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
DAC
2009
ACM
15 years 4 months ago
A physical unclonable function defined using power distribution system equivalent resistance variations
For hardware security applications, the availability of secret keys is a critical component for secure activation, IC authentication and for other important applications including...
Ryan Helinski, Dhruva Acharyya, Jim Plusquellic
FCCM
2011
IEEE
331views VLSI» more  FCCM 2011»
14 years 10 months ago
Synthesis of Platform Architectures from OpenCL Programs
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
Muhsen Owaida, Nikolaos Bellas, Konstantis Dalouka...
OSDI
1994
ACM
15 years 8 months ago
PathFinder: A Pattern-Based Packet Classifier
This paper describes a pattern-based approach to building packet classifiers. One novelty of the approach is that it can be implemented efficiently in both software and hardware. ...
Mary L. Bailey, Burra Gopal, Michael A. Pagels, La...
IWMM
2000
Springer
76views Hardware» more  IWMM 2000»
15 years 10 months ago
A Region-Based Memory Manager for Prolog
We extend Tofte and Talpin's region-based model for memory management to support backtracking and cuts, which makes it suitable for use with Prolog and other logic programmin...
Henning Makholm