Sciweavers

5762 search results - page 227 / 1153
» R-tree: A Hardware Implementation
Sort
View
133
Voted
ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
16 years 17 days ago
The design and implementation of a low-latency on-chip network
— Many of the issues that will be faced by the designers of multi-billion transistor chips may be alleviated by the presence of a flexible global communication infrastructure. I...
Robert D. Mullins, Andrew West, Simon W. Moore
CGO
2005
IEEE
16 years 7 days ago
SWIFT: Software Implemented Fault Tolerance
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. Howev...
George A. Reis, Jonathan Chang, Neil Vachharajani,...
HPDC
1999
IEEE
15 years 11 months ago
Using Embedded Network Processors to Implement Global Memory Management in a Workstation Cluster
Advances in network technology continue to improve the communication performance of workstation and PC clusters, making high-performance workstation-clustercomputing increasingly ...
Yvonne Coady, Joon Suan Ong, Michael J. Feeley
ROBOCUP
1999
Springer
95views Robotics» more  ROBOCUP 1999»
15 years 11 months ago
Spatial Agents Implemented in a Logical Expressible Language
In this paper, we present a multi-layered architecture for spatial and temporal agents. The focus is laid on the declarativity of the approach, which makes agent scripts expressive...
Frieder Stolzenburg, Oliver Obst, Jan Murray, Bj&o...
ISHPC
2000
Springer
15 years 10 months ago
Implementation and Evaluation of OpenMP for Hitachi SR8000
This paper describes the implementation and evaluation of the OpenMP compiler designed for the Hitachi SR8000 Super Technical Server. The compiler performs parallelization for the ...
Yasunori Nishitani, Kiyoshi Negishi, Hiroshi Ohta,...