5762 search results - page 223 / 1153 » R-tree: A Hardware Implementation |
141
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FPL
2003
Springer
15 years 11 months ago
2003
Springer
RC6 is a symmetric-key algorithm which encrypts 128-bit plaintext blocks to 128-bit ciphertext blocks. The encryption process involves four operations: integer addition modulo 2w ,...
152
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FPL
2003
Springer
15 years 11 months ago
2003
Springer
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
209
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FPGA
2009
ACM
15 years 11 months ago
2009
ACM
This paper presents a new architecture for time-to-digital conversion enabling a time resolution of 17ps over a range of 50ns with a conversion rate of 20MS/s. The proposed archit...
142
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ISW
2001
Springer
15 years 11 months ago
2001
Springer
In this paper, we present the results of the first phase of a project aimed at implementing a full suite of IPSec cryptographic transformations in reconfigurable hardware. Full imp...
169
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HICSS
1994
IEEE
15 years 10 months ago
1994
IEEE
Shared memory architectures often have caches to reduce the number of slow remote memory accesses. The largest possible caches exist in shared memory architectures called Cache-On...