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ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
16 years 17 days ago
Physical design implementation of segmented buses to reduce communication energy
Abstract— The amount of energy consumed for interconnecting the IP-blocks is increasing significantly due to the suboptimal scaling of long wires. To limit this energy penalty, ...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
GLVLSI
2005
IEEE
132views VLSI» more  GLVLSI 2005»
16 years 6 days ago
FPGA implementation of a modular and pipelined WF scheduler for high speed OC192 networks
In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for Packet Over Sonet (POS...
Abdallah Merhebi, Otmane Aït Mohamed
ATVA
2005
Springer
131views Hardware» more  ATVA 2005»
16 years 4 days ago
An MTBDD-Based Implementation of Forward Reachability for Probabilistic Timed Automata
Multi-Terminal Binary Decision Diagrams (MTBDDs) have been successfully applied in symbolic model checking of probabilistic systems. In this paper we propose an encoding method for...
Fuzhi Wang, Marta Z. Kwiatkowska
FPGA
2005
ACM
90views FPGA» more  FPGA 2005»
16 years 3 days ago
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits
Abstract—As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are increasingly being used to implement large arithmetic-intensive applications, which ...
Andy Gean Ye, Jonathan Rose
IPPS
2003
IEEE
15 years 12 months ago
Performance Monitoring and Evaluation of a UPC Implementation on a NUMA Architecture
UPC is an explicit parallel extension of ANSI C, which has been gaining rising attention from vendors and users. In this work, we consider the low-level monitoring and experimenta...
François Cantonnet, Yiyi Yao, Smita Annared...