Sciweavers

5762 search results - page 214 / 1153
» R-tree: A Hardware Implementation
Sort
View
MSS
2003
IEEE
95views Hardware» more  MSS 2003»
15 years 12 months ago
Design and Implementation of a Block Storage Multi-Protocol Converter
We present the Block Storage Multi-Protocol Converter (BSMC) software architecture, which is able to translate and manage SCSI commands carried by different SCSI transport protoco...
Irina Gerasimov, Alexey Zhuravlev, Mikhail Pershin...
ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
13 years 9 months ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek
FPL
2009
Springer
142views Hardware» more  FPL 2009»
15 years 10 months ago
Cooperative multithreading in dynamically reconfigurable systems
Preemptive multitasking, a popular technique for timesharing of computational resources in software-based systems, faces considerable difficulties when applied to partially reconf...
Enno Lübbers, Marco Platzner
SASP
2009
IEEE
291views Hardware» more  SASP 2009»
16 years 1 months ago
A parameterisable and scalable Smith-Waterman algorithm implementation on CUDA-compatible GPUs
—This paper describes a multi-threaded parallel design and implementation of the Smith-Waterman (SM) algorithm on compute unified device architecture (CUDA)-compatible graphic pr...
Cheng Ling, Khaled Benkrid, Tsuyoshi Hamada
SBACPAD
2006
IEEE
147views Hardware» more  SBACPAD 2006»
16 years 18 days ago
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...
Daniel A. Jiménez, Gabriel H. Loh