5762 search results - page 202 / 1153 » R-tree: A Hardware Implementation |
158
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ISCAS
2007
IEEE
16 years 25 days ago
2007
IEEE
— Simple Power Analysis (SPA) was applied to an RSA processor with a high-radix Montgomery multiplier on an FPGA platform, and the different characteristics of power waveforms ca...
147
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ISCAS
2005
IEEE
16 years 4 days ago
2005
IEEE
Abstract— In this paper, we propose a novel common subexpresson elimination (CSE) method to be used for VLSI design of multiplierless finite impulse response (FIR) filter with ...
134
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ISMVL
2005
IEEE
16 years 4 days ago
2005
IEEE
In digital signal processing, we often use higher radix system to achieve high-speed computation. In such cases, we require radix converters. This paper considers the design of LU...
177
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ICPP
2000
IEEE
15 years 11 months ago
2000
IEEE
The Virtual Interface Architecture brings the benefits of low latency User-level Networking to a cluster environment. With an increasing number of communication channels created ...
136
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ARITH
1993
IEEE
15 years 10 months ago
1993
IEEE
We detail and analyse the critical techniques which may be combined in the design of fast hardware for RSA cryptography: chinese remainders, star chains, Hensel's odd divisio...