5762 search results - page 201 / 1153 » R-tree: A Hardware Implementation |
145
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FPGA
2007
ACM
16 years 22 days ago
2007
ACM
A reconfigurable logic element (LE) is developed for use in constructing a NULL Convention Logic (NCL) FPGA. It can be configured as any of the 27 fundamental NCL gates, including...
136
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ISCAS
2006
IEEE
16 years 17 days ago
2006
IEEE
— In this paper an architecture, signal reconstruction algorithm and first-ever implementation of an asynchronous delta-sigma converter are presented. The signal reconstruction ...
165
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ISCAS
2006
IEEE
16 years 17 days ago
2006
IEEE
Abstract— In this paper, we present an algorithm/architecturelevel design solution for implementing state-parallel adaptive Viterbi decoders that, compared with their Viterbi cou...
148
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CAMP
2005
IEEE
16 years 5 days ago
2005
IEEE
Abstract— In this paper, we present a system generating freeviewpoint video in real-time using multiple cameras and a PCcluster. Our system firstly reconstructs a shape model of...
172
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ISCAS
2005
IEEE
16 years 4 days ago
2005
IEEE
— Low-Density Parity-Check Convolutional Codes (LDPC-CCs) are an attractive alternative to their block-oriented counterparts, LDPC-BCs. In this paper, we introduce these codes an...