5762 search results - page 200 / 1153 » R-tree: A Hardware Implementation |
170
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VLSISP
2008
15 years 6 months ago
2008
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
152
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ISCAS
2007
IEEE
16 years 25 days ago
2007
IEEE
— The new theory of compressive sensing enables direct analog-to-information conversion of compressible signals at subNyquist acquisition rates. We develop new theory, algorithms...
157
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FPL
2003
Springer
15 years 11 months ago
2003
Springer
This paper describes the implementation of the L3 maze routing accelerator in an FPGA. L3 supports fast single-layer and multi-layer routing, preferential routing, and rip-up-and-r...
176
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ANSS
2000
IEEE
15 years 11 months ago
2000
IEEE
This work is devoted to present the design and implementation of Alfa-1, a simulated computer with educational purposes. The DEVS formalism was used to attack the complexity of th...
158
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ISCAS
2007
IEEE
16 years 25 days ago
2007
IEEE
Abstract— Approximation of Toeplitz matrices with circulant matrices is a well-known approach to reduce the computational complexity of linear equalizers. This paper presents a n...