5762 search results - page 197 / 1153 » R-tree: A Hardware Implementation |
184
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FPL
2008
Springer
15 years 8 months ago
2008
Springer
We have constructed a FPGA-based "early neural circuit simulator" to model the first two stages of stimulus encoding and processing in the rat whisker system. Rats use t...
167
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ISLPED
2010
ACM
15 years 6 months ago
2010
ACM
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
151
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AHS
2007
IEEE
15 years 6 months ago
2007
IEEE
Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...
204
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VLSISP
2008
15 years 6 months ago
2008
This paper presents the design of an embedded automated digital video surveillance system with real-time performance. Hardware accelerators for video segmentation, morphological op...
167
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ISCAS
2007
IEEE
16 years 25 days ago
2007
IEEE
Abstract— This paper describes the first VLSI implementation of lattice reduction (LR) aided multi-antenna broadcast precoding with vector perturbation. The considered LR scheme...