Sciweavers

5762 search results - page 193 / 1153
» R-tree: A Hardware Implementation
Sort
View
DATE
2009
IEEE
124views Hardware» more  DATE 2009»
16 years 1 months ago
Design and implementation of scalable, transparent threads for multi-core media processor
—In this paper, we propose a scalable and transparent parallelization scheme using threads for multi-core processor. The performance achieved by our scheme is scalable to the num...
Takeshi Kodaka, Shunsuke Sasaki, Takahiro Tokuyosh...
IPPS
2006
IEEE
16 years 17 days ago
Parallel implementation of the replica exchange molecular dynamics algorithm on Blue Gene/L
The Replica Exchange method is a popular approach for studying the folding thermodynamics of small to modest size proteins in explicit solvent, since it is easily parallelized. Ho...
Maria Eleftheriou, Aleksandr Rayshubskiy, Jed W. P...
SBACPAD
2003
IEEE
135views Hardware» more  SBACPAD 2003»
15 years 11 months ago
Adaptive Compressed Caching: Design and Implementation
In this paper, we reevaluate the use of adaptive compressed caching to improve system performance through the reduction of accesses to the backing stores. We propose a new adaptab...
Rodrigo S. de Castro, Alair Pereira do Lago, Dilma...
ISCA
2002
IEEE
82views Hardware» more  ISCA 2002»
15 years 11 months ago
Increasing Processor Performance by Implementing Deeper Pipelines
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between ...
Eric Sprangle, Doug Carmean
CAV
2010
Springer
154views Hardware» more  CAV 2010»
15 years 10 months ago
Verifying Low-Level Implementations of High-Level Datatypes
For efficiency and portability, network packet processing code is typically written in low-level languages and makes use of bit-level operations to compactly represent data. Althou...
Christopher L. Conway, Clark Barrett