Sciweavers

5762 search results - page 189 / 1153
» R-tree: A Hardware Implementation
Sort
View
ASAP
2009
IEEE
98views Hardware» more  ASAP 2009»
15 years 4 months ago
A Power-Scalable Switch-Based Multi-processor FFT
This paper examines the architecture, algorithm and implementation of a switch-based multi-processor realization of the fast Fourier transform (FFT). The architecture employs M pr...
Bassam Jamil Mohd, Earl E. Swartzlander Jr.
DPHOTO
2009
108views Hardware» more  DPHOTO 2009»
15 years 4 months ago
IDEAL: an image pre-processing architecture for high-end professional DSC applications
We developed and implemented a flexible image pre-processing concept to achieve an image sub-system for top-end professional digital still camera applications that ensures the hig...
Auke van der Heide, Takashi Urano, Frank Polderdij...
TVCG
2012
186views Hardware» more  TVCG 2012»
13 years 9 months ago
Topology Verification for Isosurface Extraction
—The broad goals of verifiable visualization rely on correct algorithmic implementations. We extend a framework for verification of isosurfacing implementations to check topologi...
Tiago Etiene, Luis Gustavo Nonato, Carlos Eduardo ...
CCS
2007
ACM
16 years 21 days ago
Compact FPGA implementations of QUAD
QUAD is a stream cipher whose provable security relies on the hardness of solving systems of multivariate quadratic equations. This paper explores FPGA implementations of the stre...
David Arditti, Côme Berbain, Olivier Billet,...
SBACPAD
2006
IEEE
148views Hardware» more  SBACPAD 2006»
16 years 16 days ago
Scalable Parallel Implementation of Bayesian Network to Junction Tree Conversion for Exact Inference
We present a scalable parallel implementation for converting a Bayesian network to a junction tree, which can then be used for a complete parallel implementation for exact inferen...
Vasanth Krishna Namasivayam, Animesh Pathak, Vikto...