5762 search results - page 176 / 1153 » R-tree: A Hardware Implementation |
156
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ISCAS
2005
IEEE
16 years 3 days ago
2005
IEEE
—A high-throughput hardware architecture and FPGA implementation of the 64-bit NESSIE proposal, MISTY1 block cipher, is presented in this paper. This architecture, in contrast to...
172
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FPL
2004
Springer
15 years 12 months ago
2004
Springer
Real-time performance of adaptive digital signal processing algorithms is required in many applications but it often means a high computational load for many conventional processor...
183
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HYBRID
2004
Springer
15 years 12 months ago
2004
Springer
In this paper, we introduce a parametric semantics for timed controllers called the Almost ASAP semantics. This semantics is a relaxation of the usual ASAP3 semantics (also called ...
152
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ISQED
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper presents an electrical and thermal performance analysis of System-in-a-Package (SiP) memory/logic implementation platform based on ChipLaminate-Chip (CLC) technology. I...
163
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ECOOP
2010
Springer
15 years 11 months ago
2010
Springer
ncy Abstractions on x86-TSO Scott Owens University of Cambridge Abstract. With the rise of multi-core processors, shared-memory concurrency has become a widespread feature of compu...