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DATE
2009
IEEE
149views Hardware» more  DATE 2009»
16 years 1 months ago
High level H.264/AVC video encoder parallelization for multiprocessor implementation
— H.264/AVC (Advanced Video Codec) is a new video coding standard developed by a joint effort of the ITU-TVCEG and ISO/IEC MPEG. This standard provides higher coding efficiency r...
Hajer K. Zrida, Abderrazek Jemai, Ahmed C. Ammari,...
DATE
2007
IEEE
97views Hardware» more  DATE 2007»
16 years 25 days ago
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...
Abbas Sheibanyrad, Ivan Miro Panades, Alain Greine...
DSD
2007
IEEE
116views Hardware» more  DSD 2007»
16 years 25 days ago
Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation
This paper focuses on numerical function generators (NFGs) based on k-th order polynomial approximations. We show that increasing the polynomial order k reduces significantly the...
Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler
DATE
2006
IEEE
125views Hardware» more  DATE 2006»
16 years 17 days ago
Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys)
In this paper we analyze a 3D image rendering algorithm and the different mapping schemes to implement it in a SIMD reconfigurable architecture. 3D image render is highly computat...
Javier Davila, Alfonso de Torres, Jose Manuel Sanc...
DATE
2006
IEEE
121views Hardware» more  DATE 2006»
16 years 17 days ago
Analysis of the impact of bus implemented EDCs on on-chip SSN
In this paper we analyze the impact of error detecting codes, implemented on an on-chip bus, on the on-chip simultaneous switching noise (SSN). First, we analyze in detail how SSN...
Daniele Rossi, Carlo Steiner, Cecilia Metra