5762 search results - page 170 / 1153 » R-tree: A Hardware Implementation |
164
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ISCAS
1999
IEEE
15 years 10 months ago
1999
IEEE
The authors present a multiplication algorithm for low power implementation of digital filters on CMOS based digital signal processing systems. The algorithm decomposes individual...
221
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FPL
2006
Springer
15 years 10 months ago
2006
Springer
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
203
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TSP
2008
15 years 6 months ago
2008
This paper presents a systematic high-speed VLSI implementation of the discrete wavelet transform (DWT) based on hardware-efficient parallel FIR filter structures. High-speed 2-D D...
196
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VLSID
2004
IEEE
16 years 6 months ago
2004
IEEE
We present a new design of an Embedded Speech Recognition System. It combines the aspects of both hardware and software design to implement a speaker dependent, isolated word, sma...
163
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DFT
2003
IEEE
15 years 11 months ago
2003
IEEE
The implementation of imaging arrays for System-On-a-Chip (SOC) is aided by using faulttolerant light sensors. Fault-tolerant redundancy in an Active Pixel Sensor (APS) is obtaine...