5762 search results - page 167 / 1153 » R-tree: A Hardware Implementation |
209
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DFT
2006
IEEE
16 years 16 days ago
2006
IEEE
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
162
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PDP
2010
IEEE
15 years 10 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
157
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HPCC
2009
Springer
15 years 10 months ago
2009
Springer
Abstract--Transactional Memory (TM) is an emerging technology which promises to make parallel programming easier. However, to be efficient, underlying TM system should protect only...
181
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HIPEAC
2010
Springer
15 years 8 months ago
2010
Springer
The optimistic nature of Transactional Memory (TM) systems can lead to the concurrent execution of transactions that are later found to conflict. Conflicts degrade scalability, a...
168
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ICPP
2009
IEEE
16 years 1 months ago
2009
IEEE
—In an attempt to increase the performance/cost ratio, large compute clusters are becoming heterogeneous at multiple levels: from asymmetric processors, to different system archi...