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IEEEPACT
2009
IEEE
16 years 1 months ago
Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning
—Performance degradation of memory-intensive programs caused by the LRU policy’s inability to handle weaklocality data accesses in the last level cache is increasingly serious ...
Qingda Lu, Jiang Lin, Xiaoning Ding, Zhao Zhang, X...
MTV
2007
IEEE
121views Hardware» more  MTV 2007»
16 years 23 days ago
Chico: An On-chip Hardware Checker for Pipeline Control Logic
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
Andrew DeOrio, Adam Bauserman, Valeria Bertacco
GECCO
2005
Springer
232views Optimization» more  GECCO 2005»
16 years 5 hour ago
A hardware pipeline for function optimization using genetic algorithms
Genetic Algorithms (GAs) are very commonly used as function optimizers, basically due to their search capability. A number of different serial and parallel versions of GA exist. ...
Malay Kumar Pakhira, Rajat K. De
ACRI
2004
Springer
15 years 12 months ago
Optimizing the Behavior of a Moving Creature in Software and in Hardware
We have investigated a problem where the goal is to find automatically the best rule for a cell in the cellular automata model. The cells are either of type OBSTACLE, EMPTY or CRE...
Mathias Halbach, Wolfgang Heenes, Rolf Hoffmann, J...
DATE
2010
IEEE
107views Hardware» more  DATE 2010»
15 years 11 months ago
An error-correcting unordered code and hardware support for robust asynchronous global communication
A new delay-insensitive data encoding scheme for global asynchronous communication is introduced. The goal of this work is to combine the timing-robustness of delay-insensitive (i....
Melinda Y. Agyekum, Steven M. Nowick