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ANNPR
2006
Springer
15 years 8 months ago
A Convolutional Neural Network Tolerant of Synaptic Faults for Low-Power Analog Hardware
Abstract. Recently, the authors described a training method for a convolutional neural network of threshold neurons. Hidden layers are trained by by clustering, in a feed-forward m...
Johannes Fieres, Karlheinz Meier, Johannes Schemme...
WSCG
2004
154views more  WSCG 2004»
15 years 7 months ago
Emulating an Offline Renderer by 3D Graphics Hardware
3D design software has since long employed graphics chips for low-quality real-time previewing. But their dramatically increased computing power now paves the way to accelerate th...
Jörn Loviscach
IJNSEC
2008
106views more  IJNSEC 2008»
15 years 6 months ago
Parallel Hardware Architectures for the Cryptographic Tate Pairing
Identity-based cryptography uses pairing functions,which are sophisticated bilinear maps defined on elliptic curves.Computing pairings efficiently in software is presently a relev...
Guido Marco Bertoni, Luca Breveglieri, Pasqualina ...
TACO
2008
130views more  TACO 2008»
15 years 6 months ago
Efficient hardware code generation for FPGAs
r acceptance of FPGAs as a computing device requires a higher level of programming abstraction. ROCCC is an optimizing C to HDL compiler. We describe the code generation approach i...
Zhi Guo, Walid A. Najjar, Betul Buyukkurt
CGF
2004
94views more  CGF 2004»
15 years 6 months ago
Hardware-Accelerated Rendering of Photo Hulls
This paper presents an efficient hardware-accelerated method for novel view synthesis from a set of images or videos. Our method is based on the photo hull representation, which i...
Ming Li, Marcus A. Magnor, Hans-Peter Seidel