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SPAA
2010
ACM
15 years 11 months ago
Simplifying concurrent algorithms by exploiting hardware transactional memory
We explore the potential of hardware transactional memory (HTM) to improve concurrent algorithms. We illustrate a number of use cases in which HTM enables significantly simpler c...
Dave Dice, Yossi Lev, Virendra J. Marathe, Mark Mo...
RT
2001
Springer
15 years 11 months ago
Hardware-Accelerated from-Region Visibility Using a Dual Ray Space
This paper describes a novel from-region visibility algorithm, the unique properties of which allow conducting remote walkthroughs in very large virtual environments, without prepr...
Vladlen Koltun, Yiorgos Chrysanthou, Daniel Cohen-...
ICRA
2000
IEEE
180views Robotics» more  ICRA 2000»
15 years 11 months ago
Interactive Motion Planning Using Hardware-Accelerated Computation of Generalized Voronoi Diagrams
We present techniques for fast motion planning by using discrete approximations of generalized Voronoi diagrams, computed with graphics hardware. Approaches based on this diagram ...
Kenneth E. Hoff III, Tim Culver, John Keyser, Ming...
EVOW
2006
Springer
15 years 10 months ago
Optimisation of Constant Matrix Multiplication Operation Hardware Using a Genetic Algorithm
Abstract. The efficient design of multiplierless implementations of constant matrix multipliers is challenged by the huge solution search spaces even for small scale problems. Prev...
Andrew Kinane, Valentin Muresan, Noel E. O'Connor
FDTC
2006
Springer
117views Cryptology» more  FDTC 2006»
15 years 10 months ago
DPA on Faulty Cryptographic Hardware and Countermeasures
Abstract. Balanced gates are an effective countermeasure against power analysis attacks only if they can be guaranteed to maintain their power balance. Traditional testing and reli...
Konrad J. Kulikowski, Mark G. Karpovsky, Alexander...