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CODES
2006
IEEE
16 years 11 days ago
Generic netlist representation for system and PE level design exploration
Designer productivity and design predictability are vital factors for successful embedded system design. Shrinking time-to-market and increasing complexity of these systems requir...
Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah,...
ESCIENCE
2006
IEEE
16 years 11 days ago
Characterization of Computational Grid Resources Using Low-Level Benchmarks
An important factor that needs to be taken into account by end-users and systems (schedulers, resource brokers, policy brokers) when mapping applications to the Grid, is the perfo...
George Tsouloupas, Marios D. Dikaiakos
FCCM
2006
IEEE
125views VLSI» more  FCCM 2006»
16 years 11 days ago
A Multithreaded Soft Processor for SoPC Area Reduction
The growth in size and performance of Field Programmable Gate Arrays (FPGAs) has compelled System-on-aProgrammable-Chip (SoPC) designers to use soft processors for controlling sys...
Blair Fort, Davor Capalija, Zvonko G. Vranesic, St...
HPDC
2006
IEEE
16 years 11 days ago
Exploring I/O Strategies for Parallel Sequence-Search Tools with S3aSim
Parallel sequence-search tools are rising in popularity among computational biologists. With the rapid growth of sequence databases, database segmentation is the trend of the futu...
Avery Ching, Wu-chun Feng, Heshan Lin, Xiaosong Ma...
ISCAS
2006
IEEE
122views Hardware» more  ISCAS 2006»
16 years 10 days ago
256-channel integrated neural interface and spatio-temporal signal processor
Abstract- We present an architecture and VLSI implemen- Various strategies in the analysis of spatio-temporal dynamtation of a distributed neural interface and spatio-temporal ics ...
J. N. Y. Aziz, Roman Genov, B. R. Bardakjian, M. D...
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