5762 search results - page 1063 / 1153 » R-tree: A Hardware Implementation |
191
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ECBS
1996
IEEE
15 years 10 months ago
1996
IEEE
Naval Surface Warfare Center Dahlgren Division; under joint sponsorship of the Office of Naval Research; the Naval Command, Control, and Ocean Surveillance Center; and the Naval S...
218
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SIGMETRICS
1996
ACM
15 years 10 months ago
1996
ACM
This paper describes Embra, a simulator for the processors, caches, and memory systems of uniprocessors and cache-coherent multiprocessors. When running as part of the SimOS simul...
221
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PVM
1997
Springer
15 years 10 months ago
1997
Springer
The extremely low latencies and high bandwidth results achievable with the Scalable Coherent Interface SCI at lowest level encourages its integration into existing Message Passin...
160
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ICCAD
1994
IEEE
15 years 10 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
162
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SIGMETRICS
1992
ACM
15 years 10 months ago
1992
ACM
To cope with the increasing difference between processor and main memory speeds, modern computer systems use deep memory hierarchies. In the presence of such hierarchies, the perf...