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ASYNC
2000
IEEE
122views Hardware» more  ASYNC 2000»
15 years 10 months ago
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen...
FCCM
2000
IEEE
162views VLSI» more  FCCM 2000»
15 years 10 months ago
StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox
Simplifying the programming models is paramount to the success of reconfigurable computing. We apply the principles of object-oriented programming to the design of stream archite...
Oskar Mencer, Heiko Hübert, Martin Morf, Mich...
ICCAD
2000
IEEE
102views Hardware» more  ICCAD 2000»
15 years 10 months ago
Provably Good Global Buffering Using an Available Buffer Block Plan
To implement high-performance global interconnect without impacting the performance of existing blocks, the use of buffer blocks is increasingly popular in structured-custom and b...
Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu,...
ISCA
2000
IEEE
105views Hardware» more  ISCA 2000»
15 years 10 months ago
Multiple-banked register file architectures
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...
José-Lorenzo Cruz, Antonio González,...
ISPD
2000
ACM
113views Hardware» more  ISPD 2000»
15 years 10 months ago
Floorplan area minimization using Lagrangian relaxation
modules can be handled in constraint graphs efficiently. This Floorplan area minimization is an important problem because many modules have shape flexibilities during the floorplan...
Fung Yu Young, Chris C. N. Chu, W. S. Luk, Y. C. W...
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