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ASPDAC
2005
ACM
113views Hardware» more  ASPDAC 2005»
16 years 5 hour ago
Scalable interprocedural register allocation for high level synthesis
Abstract— The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the depart...
Rami Beidas, Jianwen Zhu
ISLPED
2005
ACM
90views Hardware» more  ISLPED 2005»
16 years 4 hour ago
Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices
This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of...
Yingmin Li, Mark Hempstead, Patrick Mauro, David B...
ISPD
2005
ACM
174views Hardware» more  ISPD 2005»
16 years 3 hour ago
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
In this paper, we present a very fast and accurate rectilinear Steiner minimal tree (RSMT)1 algorithm called FLUTE. The algorithm is an extension of the wirelength estimation appr...
Chris C. N. Chu, Yiu-Chung Wong
SIGMETRICS
2005
ACM
120views Hardware» more  SIGMETRICS 2005»
15 years 12 months ago
Automatic measurement of memory hierarchy parameters
The running time of many applications is dominated by the cost of memory operations. To optimize such applications for a given platform, it is necessary to have a detailed knowled...
Kamen Yotov, Keshav Pingali, Paul Stodghill
CAV
2005
Springer
173views Hardware» more  CAV 2005»
15 years 12 months ago
Building Your Own Software Model Checker Using the Bogor Extensible Model Checking Framework
Model checking has proven to be an effective technology for verification and debugging in hardware and more recently in software domains. We believe that recent trends in both th...
Matthew B. Dwyer, John Hatcliff, Matthew Hoosier, ...
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