5762 search results - page 1046 / 1153 » R-tree: A Hardware Implementation |
181
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ISCA
2007
IEEE
16 years 22 days ago
2007
IEEE
The negative performance impact of branch mis-predictions can be reduced by exploiting control independence (CI). When a branch mis-predicts, the wrong-path instructions up to the...
174
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MICRO
2007
IEEE
16 years 22 days ago
2007
IEEE
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
164
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MICRO
2007
IEEE
16 years 22 days ago
2007
IEEE
Aggressive technology scaling over the years has helped improve processor performance but has caused a reduction in processor reliability. Shrinking transistor sizes and lower sup...
174
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MICRO
2007
IEEE
16 years 22 days ago
2007
IEEE
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
180
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MOBIQUITOUS
2007
IEEE
16 years 22 days ago
2007
IEEE
—This paper discusses the design and implementation of an ultra low power embedded GPS receiver node for use in remote monitoring situations where battery life is of the utmost i...