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ISQED
2009
IEEE
124views Hardware» more  ISQED 2009»
16 years 1 months ago
Revisiting the linear programming framework for leakage power vs. performance optimization
— This paper revisits and extends a general linear programming(LP) formulation to exploit multiple knobs such as multi-Lgate footprint-compatible libraries and post-layout Lgateb...
Kwangok Jeong, Andrew B. Kahng, Hailong Yao
CODES
2009
IEEE
16 years 1 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...
DATE
2009
IEEE
183views Hardware» more  DATE 2009»
16 years 1 months ago
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips
Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on C...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
16 years 1 months ago
Bitstream relocation with local clock domains for partially reconfigurable FPGAs
—Partial Reconfiguration (PR) of FPGAs presents many opportunities for application design flexibility, enabling tasks to dynamically swap in and out of the FPGA without entire sy...
Adam Flynn, Ann Gordon-Ross, Alan D. George
DATE
2009
IEEE
163views Hardware» more  DATE 2009»
16 years 1 months ago
Fixed points for multi-cycle path detection
—Accurate timing analysis is crucial for obtaining the optimal clock frequency, and for other design stages such as power analysis. Most methods for estimating propagation delay ...
Vijay D'Silva, Daniel Kroening
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