5762 search results - page 1038 / 1153 » R-tree: A Hardware Implementation |
132
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ISQED
2010
IEEE
16 years 1 months ago
2010
IEEE
— Timing exceptions in IC implementation processes, especially timing verification, help reduce pessimism that arises from unnecessary timing constraints by masking non-function...
152
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ISQED
2010
IEEE
16 years 1 months ago
2010
IEEE
—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...
164
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ASPLOS
2010
ACM
16 years 1 months ago
2010
ACM
The behavior of a multithreaded program does not depend only on its inputs. Scheduling, memory reordering, timing, and low-level hardware effects all introduce nondeterminism in t...
166
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ISPASS
2009
IEEE
16 years 1 months ago
2009
IEEE
Abstract—Developing CPU scheduling algorithms and understanding their impact in practice can be difficult and time consuming due to the need to modify and test operating system ...
166
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ISQED
2009
IEEE
16 years 1 months ago
2009
IEEE
We propose a novel design flow for mismatch and processvariation aware optimization of nanoscale CMOS Active Pixel Sensor (APS) arrays. As a case study, an 8 × 8 APS array is de...