Sciweavers

5762 search results - page 1036 / 1153
» R-tree: A Hardware Implementation
Sort
View
ICCD
2004
IEEE
135views Hardware» more  ICCD 2004»
16 years 3 months ago
Design Methodologies and Architecture Solutions for High-Performance Interconnects
In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. F...
Davide Pandini, Cristiano Forzan, Livio Baldi
ICCAD
2008
IEEE
133views Hardware» more  ICCAD 2008»
16 years 3 months ago
Module locking in biochemical synthesis
—We are developing a framework for computation with biochemical reactions with a focus on synthesizing specific logical functionality, a task analogous to technology-independent...
Brian Fett, Marc D. Riedel
ICCAD
2007
IEEE
111views Hardware» more  ICCAD 2007»
16 years 3 months ago
Exploiting STI stress for performance
— Starting at the 65nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source – shallow trench isolation –...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...
ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
16 years 3 months ago
Application-specific customization of parameterized FPGA soft-core processors
Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are p...
David Sheldon, Rakesh Kumar, Roman L. Lysecky, Fra...
ICCAD
2006
IEEE
147views Hardware» more  ICCAD 2006»
16 years 3 months ago
Analysis and modeling of CD variation for statistical static timing
Statistical static timing analysis (SSTA) has become a key method for analyzing the effect of process variation in aggressively scaled CMOS technologies. Much research has focused...
Brian Cline, Kaviraj Chopra, David Blaauw, Yu Cao
« Prev « First page 1036 / 1153 Last » Next »