fects are statically generated program abstractions, that can be model checked for veriļ¬cation of assertions in a temporal program logic. In this paper we develop a type and eff...
This paper presents a unifying framework for the modeling of asynchronous pipeline circuits. A pipeline protocol is captured in a graph-based model which defines the partial order...
Manna and Pnueli have extensively shown how a mixture of first-order logic (FOL) and discrete Linear time Temporal Logic (LTL) is sufficient to precisely state verification problem...
Wireless Sensor Actuator Networks (WSANs) extend wireless sensor networks through actuation capability. Designing robust logic for WSANs however is challenging since nodes can aļ¬...
Reliability has become a serious concern as systems embrace nanometer technologies. In this paper, we propose a novel approach for organizing redundancy that provides high degree ...