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FORMATS
2003
Springer
15 years 11 months ago
Performance Analysis of Probabilistic Timed Automata Using Digital Clocks
Probabilistic timed automata, a variant of timed automata extended with discrete probability distributions, is a specification formalism suitable for describing both nondeterminis...
Marta Z. Kwiatkowska, Gethin Norman, David Parker,...
DCC
2010
IEEE
15 years 11 months ago
Tanner Graph Based Image Interpolation
This paper interprets image interpolation as a channel decoding problem and proposes a tanner graph based interpolation framework, which regards each pixel in an image as a variab...
Ruiqin Xiong, Wen Gao
DSN
2000
IEEE
15 years 11 months ago
An Automatic SPIN Validation of a Safety Critical Railway Control System
This paper describes an experiment in formal specification and validation performed in the context of an industrial joint project. The project involved an Italian company working...
Stefania Gnesi, Diego Latella, Gabriele Lenzini, C...
ATVA
2007
Springer
150views Hardware» more  ATVA 2007»
15 years 10 months ago
3-Valued Circuit SAT for STE with Automatic Refinement
Abstract. Symbolic Trajectory Evaluation (STE) is a powerful technique for hardware model checking. It is based on a 3-valued symbolic simulation, using 0,1 and X n"), where t...
Orna Grumberg, Assaf Schuster, Avi Yadgar
ATVA
2006
Springer
114views Hardware» more  ATVA 2006»
15 years 10 months ago
Selective Approaches for Solving Weak Games
Abstract. Model-checking alternating-time properties has recently attracted much interest in the verification of distributed protocols. While checking the validity of a specificati...
Malte Helmert, Robert Mattmüller, Sven Schewe