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ASPLOS
2010
ACM
16 years 1 months ago
Specifying and dynamically verifying address translation-aware memory consistency
Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation (AT) systems. Detecting bugs and faults requires a clear speciï...
Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. So...
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
16 years 1 months ago
On-chip communication architecture exploration for processor-pool-based MPSoC
— MPSoC is evolving towards processor-pool (PP)-based architectures, which employ hierarchical on-chip network for inter- and intra-PP communication. Since the design space of PP...
Young-Pyo Joo, Sungchan Kim, Soonhoi Ha
ASIAMS
2007
IEEE
16 years 27 days ago
XMulator: A Listener-Based Integrated Simulation Platform for Interconnection Networks
Simulation is perhaps the most cost-effective tool to evaluate the operation of a system under design. A flexible, easy to extend, fully object-oriented, and multilayered simulato...
Abbas Nayebi, Sina Meraji, Arash Shamaei, Hamid Sa...
GECCO
2007
Springer
155views Optimization» more  GECCO 2007»
16 years 22 days ago
The effect of user interaction mechanisms in multi-objective IGA
In this paper four mechanisms, fine and coarse grained fitness rating, linguistic evaluation and active user intervention are compared for use in the multi-objective IGA. The inte...
Alexandra Melike Brintrup, Hideyuki Takagi
CODES
2005
IEEE
16 years 5 days ago
Future processors: flexible and modular
The ability to continue increasing processor frequency and single thread performance is being severely limited by exponential increases in leakage and active power. To continue to...
Charlie Johnson, Jeff Welser