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DAC
2001
ACM
16 years 7 months ago
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive ...
Li Chen, Xiaoliang Bai, Sujit Dey
ICSE
2003
IEEE-ACM
16 years 6 months ago
The Deployer's Problem: Configuring Application Servers for Performance and Reliability
Frameworks such as J2EE are designed to simplify the process of developing enterprise applications by handling much of the complexity of concurrency, transaction, and persistence ...
Mukund Raghavachari, Darrell Reimer, Robert D. Joh...
ICSE
2005
IEEE-ACM
16 years 6 months ago
Transformations of software models into performance models
It is widely recognized that in order to make performance validation an integrated activity along the software lifecycle it is crucial to be supported from automated approaches. E...
Vittorio Cortellessa, Antinisca Di Marco, Paola In...
ICCD
2006
IEEE
131views Hardware» more  ICCD 2006»
16 years 3 months ago
Power-Constrained SOC Test Schedules through Utilization of Functional Buses
— In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the gen...
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...
CSCWD
2009
Springer
16 years 1 months ago
Random stimulus generation with self-tuning
Constrained random simulation methodology still plays an important role in hardware verification due to the limited scalability of formal verification, especially for the large an...
Yanni Zhao, Jinian Bian, Shujun Deng, Zhiqiu Kong