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DAC
2006
ACM
16 years 23 days ago
DFM: where's the proof of value?
How can design teams employ new tools and develop response methodologies yet still stay within design budgets? How much effort does it require to be an early adopter and what kind...
Shishpal Rawat, Raul Camposano, A. Kahng, Joseph S...
IV
2005
IEEE
142views Visualization» more  IV 2005»
16 years 12 days ago
Beyond Guidelines: What Can We Learn from the Visual Information Seeking Mantra?
The field of information visualization offers little methodological guidance to practitioners who seek to design novel systems. Though many sources describe the foundations of the...
Brock Craft, Paul A. Cairns
DAC
2000
ACM
16 years 7 months ago
Symbolic timing simulation using cluster scheduling
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...
Clayton B. McDonald, Randal E. Bryant
DATE
2007
IEEE
55views Hardware» more  DATE 2007»
16 years 1 months ago
Sensitivity analysis for fault-analysis and tolerance in RF front-end circuitry
RFIC reliability is fast becoming a major bottleneck in the yield and performance of modern IC systems, as process complexity and levels of integration continually increase. Due t...
Tejasvi Das, P. R. Mukund
ICCD
2007
IEEE
105views Hardware» more  ICCD 2007»
16 years 1 months ago
Circuit-level mismatch modelling and yield optimization for CMOS analog circuits
A methodology for constructing circuit-level mismatch models and performing yield optimization is presented for CMOS analog circuits. The methodology combines statistical techniqu...
Mingjing Chen, Alex Orailoglu