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185
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ASPDAC
2005
ACM
15 years 8 months ago
2005
ACM
— In this paper, a methodology for analyzing closed loop clock distribution and active deskewing networks is proposed. An active clock distribution and deskewing network is model...
168
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ASPDAC
2005
ACM
15 years 8 months ago
2005
ACM
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
176
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DATE
2005
IEEE
15 years 8 months ago
2005
IEEE
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consump...
168
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ER
2008
Springer
15 years 8 months ago
2008
Springer
The continuous growth of interest in mobile applications makes the concept of location essential to design and develop software systems. Location-based software is supposed to be a...
171
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FMCAD
2008
Springer
15 years 8 months ago
2008
Springer
Performing synthesis and verification in isolation has two undesirable consequences: (1) verification runs the risk of becoming intractable, and (2) strong sequential optimization...